The invention relates generally to the field of electrical power converters and inverters. More particularly, the invention relates to techniques for verifying that disable circuitry of parallel motor drives are functioning properly.
Large number of topographies and types of power conversion circuits are known and are in use. Many of these circuits rely upon inverter topologies for converting direct current (DC) power to control frequency alternating current (AC) power. In many topologies a rectifier or other converter is provided to receive incoming AC power, typically from the grid, and to convert the AC power to DC power that is applied to a DC bus used to feed the inverter circuitry. Such topologies are used in a variety of applications, such as for controlling the speed and operating characteristics of motors.
Motor drives utilizing inverter topologies often employ a single converter and single inverter coupled to one another by a single DC bus. Conventional inverters are formed by solid state switches provided in pairs and alternately switched between conducting and non-conducting states to provided desired output waveforms, typically of controlled frequency. Such topologies are adequate for many smaller applications, and may vary in size depending upon the power rating, frame size, voltage, and other specifications of the driven motor. However, for larger motors the components of such drives become proportionally large and expensive. It becomes attractive, then, to use alternative topologies in which multiple inverters are provided in parallel, with their outputs being joined to provide a common AC output to a load.
Such parallel inverter applications pose unique difficulties. For example, in certain circumstances it may be necessary to disable the motor drives. However, in some cases, decoupling one motor drive may affect the power delivered to parallel motor drives or to other motor drive circuitry that may be useful even though power is not being delivered to the load. Therefore, it may be useful in some circumstances to disable certain circuitry within the motor drive that will prevent the motor drive from outputting power to the load while maintaining the operability of certain control functions or other parallel motor drives in the system. In this way, useful functions of the power module may still be used while the output power to the load is disabled. Additionally, other motor drives operating in parallel may not be affected by the decoupling of one motor drive in the system. In these and other situations, it may be useful and even advisable to disable (e.g., shut down) one or more paralleled motor drives when certain unwanted conditions arise.
Moreover, in many cases it would be very useful to provide techniques to verify that the shutdown circuitry will operate properly when engaged. For example, a verification circuit may be used to periodically test the shutdown circuitry. The shutdown test may, however, tend to stress the power module circuitry or the load device, possibly leading to device failure. For pulsed motor drives, for example, rapid interruption and re-initiation of a pulse train powering the load can cause high potential differences within and between phase conductors that can lead to degradation of insulating systems, and eventually to failure of the motor or other system component. Also, interruption of actual drive power to a motor during such verification tests is generally undesirable. It may be advantageous, therefore, to provide a less disruptive system and method of testing a shutdown circuitry which may be used in a parallel motor drive system. To date, however, reliable disable-verification techniques for parallel motor drives that do not perturb the normal operation of the drive circuitry have yet to be developed or proposed.